The present invention relates to an absolute-phasing synchronization capturing circuit, and more particularly to an absolute-phasing synchronization capturing circuit for absolute-phasing a received signal phase angle to make it coincide with a transmission signal phase angle, the circuit being used with a receiver which receives a digital signal modulated by different modulation methods having different necessary C/N.
In a broadcasting receiver which receives a modulated digital signal transmitted by a hierarchical transmission method with a time sequential combination of different modulation methods having different necessary C/N, such as 8PSK modulation, QPSK modulation and BPSK modulation, to be repeated for each frame, an absolute-phasing synchronization capturing circuit absolute-phases a received signal phase angle to make it coincide with a transmission signal phase angle, by capturing a frame synchronization signal from demodulated baseband signals (hereinafter also called a symbol stream), by calculating a current received signal phase rotation angle from the signal point arrangement of the captured frame synchronization signal, and by rotating the demodulated baseband signals in a reverse phase direction in accordance with the calculated received signal phase rotation angle.
A conventional absolute-phasing synchronization capturing circuit has, as shown in FIG. 14, a demodulation circuit 1, a frame synchronism detection block 2, a frame synchronization signal generator 6, a remapper 7 made of a ROM, and a received signal phase detection block 8. The frame synchronism detection block 2 has a BPSK demapper 3, synchronism detection circuits 40 to 47, and a frame synchronization circuit 5. The received signal phase detection block 8 has delay circuits 81 and 82, a 0xc2x0/180xc2x0 phase rotation circuit 83, accumulating/adding/averaging circuits 85 and 86, and a received signal phase determining circuit 87.
The conventional absolute-phasing synchronization capturing circuit shown in FIG. 14 frequency-converts a received digital modulated signal into a signal having a predetermined intermediate frequency which is supplied to the demodulation circuit 1 to demodulate the intermediate frequency signal. The demodulation circuit 1 outputs demodulated baseband signals, e.g., baseband signals I(8) and Q(8) with the quantization bit number of 8 (numerals in the parentheses indicate the number of bits which are sometimes omitted in the following and simply written as I and Q).
The baseband signals I(8) and Q(8) are input to, for example, the BPSK demapper 3 of the frame synchronism detection block 2 in order to capture the BPSK modulated frame synchronization signal. The BPSK demapper 3 outputs a BPSK demapped bit stream B0. The BPSK demapper 3 is made of, for example, a ROM.
Mapping for each modulation method on the transmission side will be described with reference to FIG. 15. FIG. 15(a) shows a signal point arrangement for 8PSK modulation. 8PSK modulation can transmit a three-bit digital signal (a, b, c) by one symbol. There are eight combinations of bits constituting one symbol, i.e., (0, 0, 0), (0, 0, 1), . . . , (1, 1, 1). These 3-bit digital signals are converted into signal point arrangements 0 to 7 on a transmission side I-Q vector plane shown in FIG. 15(a). This conversion is called 8PSK mapping.
In the example shown in FIG. 15(a), a bit train (0, 0, 0) is converted into the signal point arrangement xe2x80x9c0xe2x80x9d, a bit train (0, 0, 1) is converted into the signal point arrangement xe2x80x9c1xe2x80x9d, a bit train (0, 1, 1) is converted into the signal point arrangement xe2x80x9c2xe2x80x9d, a bit train (0, 1, 0) is converted into the signal point arrangement xe2x80x9c3xe2x80x9d, a bit train (1, 0, 0) is converted into the signal point arrangement xe2x80x9c4xe2x80x9d, a bit train (1, 0, 1) is converted into the signal point arrangement xe2x80x9c5xe2x80x9d, a bit train (1, 1, 1) is converted into the signal point arrangement xe2x80x9c6xe2x80x9d, and a bit train (1, 1, 0) is converted into the signal point arrangement xe2x80x9c7xe2x80x9d.
FIG. 15(b) shows a signal point arrangement for QPSK modulation. QPSK modulation can transmit a two-bit digital signal (d, e) by one symbol. There are four combinations of bits constituting one symbol, i.e., (0, 0), (0, 1), (1, 0) and (1, 1). In the example shown in FIG. 15(b), a bit train (1, 1) is converted into the signal point arrangement xe2x80x9c1xe2x80x9d, a bit train (0, 1) is converted into the signal point arrangement xe2x80x9c3xe2x80x9d, a bit train (0, 0) is converted into the signal point arrangement xe2x80x9c5xe2x80x9d, and a bit train (1, 0) is converted into the signal point arrangement xe2x80x9c7xe2x80x9d. The relation between the signal point arrangement and its number of each modulation method is defined in the same manner as 8PSK modulation.
FIG. 15(c) shows a signal point arrangement for BPSK modulation. BPSK modulation can transmit a one-bit digital signal (f) by one symbol. The digital signal (1) is converted into the signal point arrangement xe2x80x9c0xe2x80x9d and the digital signal (0) is converted into the signal point arrangement xe2x80x9c4xe2x80x9d.
Next, the frame synchronization signal will be described. In the hierarchical transmission method, the frame synchronization signal modulated by BPSK having the lowest necessary C/N is transmitted. It is assumed herein that the bit stream of the frame synchronization signal constituted of 16 bits is (S0, S1, . . . , S14, S15) and each bit is transmitted starting from S0. In this case, a bit stream (0, 0, 0, 1, 0, 0, 1, 1, 0, 1, 0, 1, 1, 1, 1, 0) and a bit stream with inverted last half eight bits (0, 0, 0, 1, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 1) are alternately transmitted for each frame. In the following, the bit stream of the frame synchronization signal is also written as xe2x80x9cSYNCPATxe2x80x9d, and the bit stream with inverted last half eight bits is also written as xe2x80x9cnSYNCPATxe2x80x9d. At transmission side this bit stream is converted into either the signal point arrangement xe2x80x9c0xe2x80x9d or xe2x80x9c4xe2x80x9d by BPSK mapping shown in FIG. 15(c), and the converted symbol stream is transmitted.
In order to capture the frame synchronization signal of 16 bits, i.e., 16 symbols BPSK-modulated and transmitted, the received symbols are required to be converted into bits by BPSK demapping shown in FIG. 16(a) opposite to the mapping at the transmission side. As shown in FIG. 16(a), if the demodulated signal is received in a hatched area on the reception side I-Q vector plane, it is judged as xe2x80x9c1xe2x80x9d, whereas if it is received in an area not hatched, it is judged as xe2x80x9c0xe2x80x9d. Namely, depending upon whether the demodulated signal is received on which area among the two areas divided by a bold BPSK determining borderline of FIG. 16(a), the output is judged as xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d. This operation is called BPSK demapping.
The baseband signals I and Q are input to the BPSK demapper 3 to perform the bit conversion. The BPSK demapper 3 performs BPSK demapping and outputs a bit stream B0. In this specification, the term xe2x80x9cdemapperxe2x80x9d means a demapping circuit. The bit stream B0 is input to the synchronism detection circuit 40 which captures the bit stream of the frame synchronization signal from the bit stream B0.
Next, the synchronism detection circuit 40 will be described with reference to FIG. 17. The bit stream B0 is input to a shift register D15 and sequentially shifted up to a shift register D0. At the same time, after the logical levels of the outputs of the shift registers D15 to D0 at predetermined bits are inverted, the outputs of the shift registers D15 to D0 are input to AND gates 51 and 52. An output SYNA0 of the AND gate 51 takes a high level when the status of the shift registers D15 to D0 (D0, D1, . . . , D14, D15) becomes (0, 0, 0, 1, 0, 0, 1, 1, 0, 1, 0, 1, 1, 1, 1, 0), whereas an output SYNB0 of the AND gate 52 takes a high level when the status becomes (0, 0, 0, 1, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 1). Namely, when SYNCPAT is captured, the output SYNA0 takes the high level, and when nSYNCPAT is captured, the output SYNB0 takes the high level.
The outputs SYNNA0 and SYNB0 of the synchronism detection circuit 40 are input to the frame synchronization circuit 5 which judges that there is a frame synchronization if it confirms that SYNNA0 and SYNB0 are alternately received at a predetermined frame pitch, and outputs a frame synchronization pulse at each frame period.
Generally, in the hierarchical transmission method with a time sequential combination of different modulation methods having different necessary C/N to be repeated for each frame, header data representative of such a frame multiplexing structure is multiplexed. After it is judged that there is a frame synchronization, the header data representative of the frame multiplexing structure is extracted in response to a timing signal generated from the frame synchronization pulse output from the frame synchronization circuit 5. It is therefore possible to start processing for each modulation method only after the frame multiplexing structure is identified.
In other words, until the frame synchronization is judged, the demodulation circuit 1 operates as an 8PSK demodulation circuit. Therefore, depending upon the phase of a demodulation carrier reproduced by a carrier reproduction circuit of the demodulation circuit 1, the I and Q axes of the reception side I-Q vector plane rotate and change their phases by xcex8=45xc2x0xc3x97n (n is an integer of 0 to 7) relative to the transmission side I-Q vector plane. More specifically, depending upon the phase of the demodulation carrier, the symbol stream of the frame synchronization signal BPSK-mapped at the signal point arrangement xe2x80x9c0xe2x80x9d for the bit xe2x80x9c1xe2x80x9d and at the signal point arrangement xe2x80x9c14xe2x80x9d for the bit xe2x80x9c0xe2x80x9d shown in FIG. 15(c), may appear at the signal point arrangements xe2x80x9c0xe2x80x9d and xe2x80x9c4xe2x80x9d if xcex8=0xc2x0 same as the transmission side, at the signal point arrangements xe2x80x9c1xe2x80x9d and xe2x80x9c5xe2x80x9d if the phase rotation xcex8=45xc2x0, at the signal point arrangements xe2x80x9c2xe2x80x9d and xe2x80x9c6xe2x80x9d if the phase rotation xcex8=90, and so on. There are, therefore, eight phases at which the frame synchronization signal is demodulated. It is necessary to capture the frame synchronization signal even if it is demodulated at which phase.
Therefore, as shown in FIG. 18, the BPSK demapper 3 is constituted of BPSK demappers 30 to 37 corresponding to the phase rotations of xcex8=0xc2x0 (n=0), xcex8=45xc2x0 (n=1), xcex8=90xc2x0 (n=2), . . . , xcex8=270xc2x0 (n=6), and xcex8=315xc2x0 (n=7).
FIG. 16(b) illustrates BPSK demapping wherein the symbol list of the demodulated frame synchronization signal has the phase rotation of xcex8=45xc2x0 so that the bit xe2x80x9c1xe2x80x9d appears at the signal point arrangement xe2x80x9c1xe2x80x9d and the bit xe2x80x9c0xe2x80x9d appears at the signal point arrangement xe2x80x9c5xe2x80x9d. The bold BPSK determining borderline shown in FIG. 16(b) rotates by 45xc2x0 in the counter-clockwise direction relative to the bold BPSK determining borderline of BPSK demapping with the same phase as the transmission side shown in FIG. 16(a). By using such a BPSK demapper, the frame synchronization signal rotated by xcex8=45xc2x0 can be captured stably. This output of the BPSK demapper 3 corresponds to an output B1 shown in FIG. 14. B2 to B7 are outputs of the BPSK demapper 3 corresponding to xcex8=45xc2x0xc3x97n (n is an integer of 2 to 7).
The circuit structures of the synchronism detection circuits 41 to 47 are the same as the synchronism detection circuit 40. Since the synchronism detection circuits 40 to 47 are provided, the frame synchronization signal can be captured by at least one or more of the synchronism detection circuits 40 to 47, irrespective of the phase rotation of the baseband signals caused by the phase of the reproduction carrier reproduced by the carrier reproduction circuit of the demodulation circuit 1. The synchronism detection circuit captured the frame synchronization signal outputs SYNAn or SYNBn (n is an integer of 0 to 7) in accordance with the pattern (SYNCPAT or nSYNCPAT) of the captured frame synchronization signal.
The SYNAn and SYNBn signals are received by OR gates 53 and 54 of the frame synchronization circuit 5 shown in FIGS. 19(a) and 19(b). If it is confirmed that a logical sum SYNA of SYNAn of the OR gate 53 and a logical sum SYNB of SYNBn of the OR gate 54 are alternately received at a predetermined frame pitch, it is judged that there is a frame synchronization and a frame synchronization pulse is output at each frame period.
The operation of the frame synchronism detection block 2 shown in FIG. 14 which captures the frame synchronization signal and outputs the frame synchronization pulse has been described above. Next, absolute-phasing will be described in which a currently received signal phase rotation angle is calculated from the signal point arrangement of the captured frame synchronization signal, and the demodulated baseband signals are rotated in a reverse phase direction in accordance with the calculated phase rotation angle.
The symbol stream of the frame synchronization signal obtained from the baseband signals BPSK-mapped and transmitted from the transmission side and demodulated by the demodulation circuit 1, is demapped by the BPSK demapper 3 into a bit xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d. The phase difference between the symbol streams of the frame synchronization signals demapped to the bits xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d is 180xc2x0. Therefore, if the phase of the symbol stream of the frame synchronization signal to be demapped to the bit xe2x80x9c0xe2x80x9d is rotated by 180xc2x0, symbol streams all demapped to the bit xe2x80x9c1xe2x80x9d can be obtained.
By calculating an average of symbol streams all demapped to the bit xe2x80x9c1xe2x80x9d, the reception side signal point arrangement for the BPSK bit xe2x80x9c1xe2x80x9d can be obtained. A phase difference between the obtained reception side signal point arrangement for the BPSK bit xe2x80x9c1xe2x80x9d and the transmission side signal point arrangement xe2x80x9c0xe2x80x9d mapped for the bit xe2x80x9c1xe2x80x9d is calculated. This phase difference is used as the reception signal phase rotation angle xcex8, and the demodulated baseband signals are rotated in a reverse phase direction to realize the absolute-phasing of the baseband signals.
A conventional absolute-phasing synchronization capturing circuit shown in FIG. 14 will further be described. Upon reception of the frame synchronization pulse output from the frame synchronization circuit 5, the frame synchronization signal generator 6 generates a bit stream of the captured frame synchronization signal corresponding to its pattern of SYNCPAT or nSYNCPAT. The generated bit stream is supplied to the 0xc2x0/180xc2x0 phase rotation circuit 83 of the received signal phase detection block 8. In accordance with the bit xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d of the supplied bit stream, the 0xc2x0/180xc2x0 phase rotation circuit 83 rotates the phase by 180xc2x0 if the bit is xe2x80x9c0xe2x80x9d, does not rotate the phase if the bit is xe2x80x9c1xe2x80x9d, and outputs the bit stream.
The timings of the bit stream of the reproduced frame synchronization signal supplied from the frame synchronization signal generator 6 and the symbol stream of the frame synchronization signal are adjusted by the delay circuits 81 and 82 to make them coincide with each other at the inputs of the 0xc2x0/180xc2x0 phase rotation circuit 83. Gates of the delay circuits 81 and 82 are opened upon reception of a frame synchronization signal section signal supplied from the frame synchronization signal generator 6, and symbol streams DI(8) and DQ(8) of the frame synchronization signals output from the delay circuits 81 and 82 are rotated by 180xc2x0 in phase by the 0xc2x0/180xc2x0 phase rotation circuit 83 if the bit stream is xe2x80x9c0xe2x80x9d and supplied to the accumulating/adding/averaging circuits 85 and 86.
FIG. 20(a) shows the signal point arrangement of the frame synchronization signal received at the received signal phase rotation angle of xcex8=0xc2x0, and FIG. 20(b) shows the signal point arrangement of the symbol streams VI(8) and VQ(8) after converted by the 0xc2x0/180xc2x0 phase rotation circuit 83. The symbol streams VI(8) and VQ(8) are supplied to the accumulating/adding/averaging circuits 85 and 86 to be subjected to an adding/averaging operation in a predetermined section, and the symbol streams AVI(8) and AVQ(8) subjected to the adding/averaging operation in the predetermined section are output. This adding/averaging operation for the symbol streams VI(8) and VQ(8) is performed in order to reliably acquire the signal point arrangement even if the received baseband signals change slightly their phase because of a degraded reception C/N or even if the amplitudes thereof vary.
The accumulating/adding/averaging circuits 85 and 86 obtain reception signal points [AVI(8), AVQ(8)] for the BPSK mapped bit xe2x80x9c1xe2x80x9d. Next, the reception signal points [AVI(8), AVQ(8)] are input to the received signal phase determining circuit 87 made of a ROM which obtains a 3-bit phase rotation signal RT(3) corresponding to the phase rotation angle, by using a reception signal phase determining table shown in FIG. 21. xe2x80x9c0xe2x80x9d to xe2x80x9c7xe2x80x9d shown in FIG. 21 indicate a decimal representation of the phase rotation signal RT(3). For example, if the received signal phase rotation angle is xcex8=0xc2x0 as shown in FIG. 20(a), the phase rotation signal for the signal points AVI(8) and AVQ(8) is judged as xe2x80x9c0xe2x80x9d by the received signal phase determining table. Therefore, (0, 0, 0) is output as the phase rotation signal RT(3). If the received signal phase rotation angle is xcex8=45xc2x0, then the phase rotation signal RT(3) is xe2x80x9c1xe2x80x9d so that (0, 0,1) is output as the phase rotation signal RT(3).
Upon reception of this phase rotation signal RT(3), the remapper 7 made of a ROM rotates the phases of the baseband signals I(8) and Q(8) in accordance with the phase rotation signal RT(3) to thereby realize the absolute-phasing.
The operation of the remapper 7 will be described further. The remapper 7 is a phase conversion circuit for making the signal point arrangement of received baseband signals coincide with that of the transmission side. The received signal phase detection block 8 calculates the received signal phase rotation angle xcex8 and supplies the phase rotation signal RT(3) corresponding to the received signal phase rotation angle xcex8 to the remapper 7. The phase rotation signal RT(3) takes an integer of 0 to 7, and the relation to the phase rotation angle xcex8 is defined by the following equation (1):
RT(3)=xcex8/45xe2x80x83xe2x80x83(1)
where xcex8=nxc2x745xc2x0 and n is an integer of 0 to 7.
The absolute-phasing for the baseband signal is performed by a reverse phase rotation (xe2x88x92xcex8) relative to the phase rotation angle xcex8. Therefore, the remapper 7 rotates the phases of the input baseband signals I and Q by an angle xcfx86 (=xe2x88x92xcex8) in accordance with the following equations (2) and (3) and outputs the absolute-phased baseband signals Ixe2x80x2(8) and Qxe2x80x2(8) (hereinafter may be written as Ixe2x80x2 and Qxe2x80x2 where applicable by omitting the bit number):
Ixe2x80x2=I cos(xcfx86)xe2x88x92Q sin(xcfx86)xe2x80x83xe2x80x83(2)
Qxe2x80x232 I sin(xcfx86)+Q cos(xcfx86)xe2x80x83xe2x80x83(3)
With the conventional absolute-phasing synchronization capturing circuit, however, the BPSK demapper is essential. If a ROM is used for the table conversion by the BPSK demapper, the memory capacity of 64 K bytes (216xc3x978 bits) is necessary. The eight synchronism detection circuits require 128 registers in total, and a coincidence detection logical circuit of a large circuit scale is required in addition to the remapper. If a ROM is used for the table conversion by the remapper, the memory capacity of 1 M bytes (219xc3x9716 bits) is necessary. The circuit scale therefore becomes large.
It is an object of the present invention to provide an absolute-phasing synchronization capturing circuit with a small circuit scale.
The absolute-phasing synchronization capturing circuit of this invention for absolute-phasing of making a reception signal phase angle coincide with a transmission signal phase angle, by capturing a frame synchronization signal and by detecting the reception signal phase angle relative to the transmission signal phase angle from the captured frame synchronization signal, comprises: phase rotating means for rotating phases of demodulated baseband signals by 45xc2x0xc3x97n (n=1, 3, 5 or 7); first phase inverting means for inverting the phases of the demodulated baseband signals; second phase inverting means for inverting phases of baseband signals phase-rotated by the phase rotating means; and selecting means for selectively outputting the demodulated baseband signals, the baseband signals phase-rotated by the phase rotating means, baseband signals output from the first phase inverting means, and baseband signals output from the second phase inverting means, in accordance with the reception signal phase rotation angle relative to the transmission signal phase, wherein most significant bits are extracted from the demodulated baseband signals and from the baseband signals phase-rotated by the phase rotating means, and the frame synchronization signal is captured by using the extracted most significant bits.
According to the absolute-phasing synchronization capturing circuit of this invention, the demodulated baseband signals, the baseband signals phase-rotated by the phase rotating means, baseband signals output from the first phase inverting means, and baseband signals output from the second phase inverting means are selectively output in accordance with the reception signal phase rotation angle relative to the transmission signal phase, to thereby realize the absolute phasing of the reception signal. Most significant bits are extracted from the demodulated baseband signals and from the baseband signals phase-rotated by the phase rotating means, and the frame synchronization signal is captured by using the extracted most significant bits.
The phase rotating means performs a phase rotation by a fixed angle so that the structure thereof can be simplified and the phase rotating means can be configured by using a memory circuit and a logic circuit. As compared with table conversion using a memory circuit to be performed by a conventional necessary remapper, a necessary memory capacity can be reduced by xe2x85x9 of the conventional memory capacity of 219xc3x9716 bits. A conventionally necessary BPSK demapper is not necessary. As compared with table conversion using a memory circuit to be performed by a PSK demapper, a memory capacity of 216xc3x9716 bits can be reduced.
Instead of extracting most significant bits from the demodulated baseband signals and from the baseband signals phase-rotated by the phase rotating means, they may be extracted from the baseband signals output from the first and second phase inverting means.
The absolute-phasing synchronization capturing circuit of this invention for absolute-phasing of making a reception signal phase angle coincide with a transmission signal phase angle, by capturing a frame synchronization signal and by detecting the reception signal phase angle relative to the transmission signal phase angle from the captured frame synchronization signal, comprises: a synchronism detection circuit for detecting a bit stream of a first frame synchronization signal alternately extracted from demodulated baseband signals, a bit stream of a second frame synchronization signal obtained by inverting sings of last half bits of the bit stream of the first frame synchronization signal, a bit stream of a third frame synchronization signal obtained by inverting a sign of each bit of the bit stream of the first frame synchronization signal, and a bit stream of a fourth frame synchronization signal obtained by inverting a sign of each bit of the bit stream of the second frame synchronization signal, wherein the frame synchronization signal is captured in accordance with an output from the synchronism detection circuit.
In the absolute-phasing synchronization capturing circuit, the outputs for the reception signal phase rotation angles of xcex8=0xc2x0 and 180xc2x0, xcex8=45xc2x0 and 225xc2x0, xcex8=90xc2x0 and 270xc2x0, and xcex8=135xc2x0 and 315xc2x0 have a logical inversion relation. Therefore, the synchronism detection circuit of the absolute-phasing synchronization capturing circuit detects only the bit streams of the extracted first and second frame synchronization signals, the bit stream of the third frame synchronization signal obtained by inverting the sign of each bit of the bit stream of the first frame synchronization signal, and the bit stream of the fourth frame synchronization signal obtained by inverting the sign of each bit of the bit stream of the second frame synchronization signal. The number of necessary synchronism detection circuits is a half of that of the conventional circuit, and the number of necessary shift resisters is a half of that of the conventional circuit. The circuit scale of the circuit can therefore be reduced.
The absolute-phasing synchronization capturing circuit of this invention for absolute-phasing of making a reception signal phase angle coincide with a transmission signal phase angle, by capturing a frame synchronization signal and by detecting the reception signal phase rotation angle relative to the transmission signal phase angle from the captured frame synchronization signal, comprises: accumulating/adding/subtracting/averaging means for extracting a bit stream of a frame synchronization signal from demodulated baseband signals over a frame synchronization signal section, performing an adding operation if the extracted bit stream of the frame synchronization signal has a logical level xe2x80x9c1xe2x80x9d, performing a subtracting operation if the extracted bit stream of the frame synchronization signal has a logical level xe2x80x9c0xe2x80x9d, and averaging adding/subtracting operation results, wherein a phase of a reception signal is determined in accordance with an out put from the accumulating/adding/subtracting/averaging means, and phases of the demodulated baseband signals are rotated by an amount of the determined phase.
A conventional 0xc2x0/180xc2x0 phase rotation circuit using table conversion by a memory circuit or an arithmetic circuit is not necessary so that the circuit scale can be reduced. If the conventional 0xc2x0/180xc2x0 phase rotation circuit utilizes table conversion by a memory circuit, the memory capacity of 216xc3x9716 bits can be reduced and the circuit scale can be reduced.